(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of forming a self-aligned elevated transistor using the technique of silicon epitaxial growth in the manufacture of integrated circuits.
(2) Description of the Prior Art
Shallow trench isolation (STI) will be employed widely in current and future integrated circuit technologies to provide sufficient isolation between neighboring devices. However, there are a number of problematic issues in STI processes including xe2x80x9chump effectsxe2x80x9d and chemical mechanical polishing (CMP) induced dishing over wide trenches that must be resolved prior to its further and wider applications. The STI corner represents an abrupt transition from the transistor active area to isolation. The gate polysilicon wraparound of a sharp trench corner causes a separate conduction characteristic of the corner resulting in a xe2x80x9cdouble humpxe2x80x9d in the transistor drain current-gate voltage characteristics. It is desired to void the problem of the xe2x80x9chump effects.xe2x80x9d Another problem with STI processes is that the packing density of integrated circuits will be limited by the dimensions of the isolation trenches. It is desired to fabricate an integrated circuit without the drawbacks of the STI process.
U.S. Pat. No. 4,749,441 to Christenson et al teaches a method of selective epitaxial growth (SEG) to form elevated source/drain regions. However, the gate electrode is not formed by self-aligning techniques. U.S. Pat. No. 5,686,343 to Lee teaches forming an epitaxial layer and patterning it to provide an active area. U.S. Pat. No. 5,780,343 discloses the formation of an SEG layer within a trench and forming a gate thereover. U.S. Pat. No. 5,681,776 to Hebert et al teaches SEG within a trench and then oxidation of the SEG regions to form trench isolation. U.S. Pat. No. 5,453,396 to Gonzalez et al discloses a SEG process for a DRAM.
A principal object of the present invention is to provide an effective and very manufacturable method of forming a self-aligned elevated transistor in the fabrication of an integrated circuit.
Another object of the present invention is to provide a method of forming a self-aligned elevated transistor using selective epitaxial growth in the fabrication of an integrated circuit.
Yet another object of the present invention is to provide a method of forming a self-aligned elevated transistor wherein there is absolute control over junction depth.
A further object of the invention is to provide a method of forming a self-aligned elevated transistor using selective epitaxial growth wherein there is absolute control over junction depth.
A still further object of the invention is to provide a method of forming a self-aligned elevated transistor wherein the packing density of integrated circuits is not limited by the dimension of isolation trenches.
Yet another object of the present invention is to provide a method of forming a self-aligned elevated transistor without the use of shallow trench isolation.
A still further object of the invention is to provide a method of forming a self-aligned elevated transistor using selective epitaxial growth wherein the packing density of integrated circuits is not limited by the dimension of isolation trenches.
In accordance with the objects of this invention the method of forming a a self-aligned elevated transistor using selective epitaxial growth wherein the packing density of integrated circuits is not limited by the dimension of isolation trenches is achieved. An oxide layer is provided overlying a semiconductor substrate. The oxide layer is etched through to the semiconductor substrate to form a trench having a lower portion contacting the substrate and an upper portion having a width larger than the width of the lower portion. A silicon layer is grown within the trench using selective epitaxial growth wherein the silicon layer fills the lower portion and partially fills the upper portion wherein the thickness of the silicon layer partially filling the upper portion is controlled. A liner oxide layer is deposited overlying the oxide layer and the silicon layer within the trench. Nitride spacers are formed on the sidewalls of the trench over the liner oxide layer. The liner oxide is removed where it is not covered by the nitride spacers overlying the silicon layer. A gate oxide layer is grown overlying the silicon layer within the trench. A polysilicon layer is deposited overlying the oxide layer and within the trench and etched back to form a gate electrode within the trench between the nitride spacers. The nitride spacers are etched away where they are not covered by the gate electrode leaving thin nitride spacers on sidewalls of the gate electrode and exposing the liner oxide overlying the silicon layer at edges of the trench. The exposed liner oxide is etched away. Ions are implanted into the silicon layer at the edges of the trench whereby source and drain pockets are formed within the silicon layer and wherein the controlled thickness of the silicon layer partially filling the upper portion of the trench corresponds to a desired junction depth of the source/drain pockets. The gate electrode and source/drain pockets are silicided. A dielectric layer is deposited overlying the oxide layer and silicided source/drain pockets and silicided gate electrode within the trench wherein the gate electrode and the source/drain pockets form the self-aligned elevated transistor in the fabrication of an integrated circuit.
Also, according to the objects of the invention, a new self-aligned elevated transistor is achieved. An oxide layer overlies a semiconductor substrate. A silicon layer fills a lower portion of a trench through the oxide layer and partially fills an upper portion of the trench wherein the lower portion of the trench contacts the semiconductor substrate and has a width smaller than a width of the upper portion of the trench. A polysilicon gate electrode overlies a center portion of the silicon layer having a gate oxide layer therebetween. Source/drain pockets lie within the silicon layer at edge portions of the silicon layer not covered by the polysilicon gate electrode. A dielectric layer overlies the oxide layer and the gate electrode and source/drain pockets within the trench to complete elevated transistor in an integrated circuit device.